Cross-Domain Power Control Circuit

ABSTRACT

A cross-domain power control circuit is disclosed. The circuit includes a first circuit branch having a first transistor coupled to a first supply voltage node and a second circuit branch having a second transistor coupled to the first supply voltage node. A third circuit branch is coupled between a second supply voltage node and a third supply voltage node. A second supply voltage conveyed on the second supply voltage node is less than a first supply voltage conveyed on the first supply voltage node. A fourth circuit branch is coupled between the first and third supply voltage nodes. In a first mode of operation, control circuitry causes the second supply voltage to be conveyed to the third supply voltage node. In a second mode of operation, the control circuitry causes the first supply voltage to be conveyed to the third supply voltage node.

BACKGROUND Technical Field

This disclosure is directed to electronic circuits, and more particularly, for circuits used to control an interface between power domains operating at different supply voltages.

Description of the Related Art

Modern integrated circuits (ICs) often times have multiple power domains with circuitry powered by different supply voltages. For example, an IC may have a first power domain having circuitry powered by a first supply voltage, and a second power domain having circuitry powered by a second supply voltage that is different from the first. This may be due in part to the fact that some circuits operate better with certain voltages than other. Thus, an IC having both analog and digital circuits implemented thereon may use a first supply voltage for the analog circuitry and a second supply voltage for the digital circuits.

Although various circuits may be implemented in different power domains, it is often times necessary for communication of circuits in these different domains to communicate with one another. Furthermore, to achieve power savings, many ICs are implemented that idle circuits can be powered down. This may at times involve powering down circuitry within one power domain, while circuitry in an adjacent power domain may remain powered on for continuing operations.

SUMMARY

A cross-domain power control circuit is disclosed. In one embodiment, the circuit includes a first circuit branch having a first transistor coupled to a first supply voltage node and a second circuit branch having a second transistor coupled to the first supply voltage node. A third circuit branch is coupled between a second supply voltage node and a third supply voltage node. A second supply voltage conveyed on the second supply voltage node is less than a first supply voltage conveyed on the first supply voltage node. A fourth circuit branch is coupled between the first and third supply voltage nodes. In a first mode of operation, control circuitry causes the second supply voltage to be conveyed to the third supply voltage node. In a second mode of operation, the control circuitry causes the first supply voltage to be conveyed to the third supply voltage node.

The third supply voltage node may receive the second supply voltage when the first supply voltage is powered down, which corresponds to operation in the first mode. When the first supply is fully powered on, the first supply voltage is provided to the third voltage node. A third mode of operation may occur when the first supply voltage is initially powered on, as the third supply voltage node ramps up from the second supply voltage to the first supply voltage. A fourth mode of operation may occur when the first supply voltage node when the first supply voltage is to be powered down, as the third supply voltage node ramps down from the first supply voltage to the second supply voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description makes reference to the accompanying drawings, which are now briefly described.

FIG. 1 is a schematic diagram of one embodiment of a cross-domain power control circuit.

FIG. 2 is a schematic diagram illustrating an arrangement of a cross-domain power control circuit in the context of two power domains.

FIG. 3 is a block diagram illustrating first and second power domains and circuitry coupling the two.

FIG. 4 is a timing diagram illustrating various modes of operation of one embodiment of a cross-domain power control circuit.

FIG. 5 is a flow diagram illustrating one embodiment of a method for operating a cross-domain power control circuit.

FIG. 6 is a block diagram of one embodiment of an example system.

Although the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described herein in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, this application is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the disclosure of the present application as defined by the appended claims.

This disclosure includes references to “one embodiment,” “a particular embodiment,” “some embodiments,” “various embodiments,” or “an embodiment.” The appearances of the phrases “in one embodiment,” “in a particular embodiment,” “in some embodiments,” “in various embodiments,” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation [entity] configured to [perform one or more tasks] is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. A “credit distribution circuit configured to distribute credits to a plurality of processor cores” is intended to cover, for example, an integrated circuit that has circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.

The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function, although it may be “configurable to” perform that function after programming.

Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Accordingly, none of the claims in this application as filed are intended to be interpreted as having means-plus-function elements. Should Applicant wish to invoke Section 112(f) during prosecution, it will recite claim elements using the “means for” [performing a function] construct.

As used herein, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”

As used herein, the phrase “in response to” describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.

As used herein, the terms “first,” “second,” etc. are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise. For example, in a register file having eight registers, the terms “first register” and “second register” can be used to refer to any two of the eight registers, and not, for example, just logical registers 0 and 1.

When used in the claims, the term “or” is used as an inclusive or and not as an exclusive or. For example, the phrase “at least one of x, y, or z” means any one of x, y, and z, as well as any combination thereof.

In the following description, numerous specific details are set forth to provide a thorough understanding of the disclosed embodiments. One having ordinary skill in the art, however, should recognize that aspects of disclosed embodiments might be practiced without these specific details. In some instances, well-known circuits, structures, signals, computer program instruction, and techniques have not been shown in detail to avoid obscuring the disclosed embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

The present disclosure is directed to a cross-domain power control circuit. Continuous supply voltage scaling in modern CMOS processes can pose a challenge for sensitive analog circuit in an analog power domain. Since analog performance may have certain requirements regarding linearity, bandwidth, lower switch-on resistance, and so on, analog supply voltages may be regulated and boosted. In some integrated circuit, a digital power supply may produce a higher analog power supply using a voltage regulator (e.g., a low dropout, or LDO regulator). While this arrangement may have some benefits, a problem may occur when the analog subsystem needs to be operational on an ‘as needed’ basis, but is otherwise powered down when not needed. In certain applications, such as an on-chip continuous measurement system, an analog subsystem (in an analog power domain) is connected to a digital subsystem by a front end transmission gate switch network. When the analog subsystem is in a power down mode (and thus the analog power supply is powered down), the front end transmission gate switch network cannot be turned off. As a result, multiple interface signals crossing from the digital power domain to the analog power domain are fed through to the analog domain. When these signals are effectively shorted by the transmission gate switch network, severe performance degradation or failure can occur during operation of the digital subsystem. Additionally, the digital signals can forward bias source bulk diodes of the PMOS devices used in the transmission gate switch network. This can cause excessive current to be drawn by the digital subsystem, which can be another source of performance failure.

The cross-domain power control circuit of the present disclosure may address these problems. In particular, signal feedthrough and digital signal shorting problems may be eliminated, while the front end switch network is not forward biased in any mode of operation.

In various embodiments, the cross-domain power control circuit is coupled to first and second supply voltage nodes associated with first and second power domains, respectively. The cross-domain power circuit also includes a third supply voltage node which can be set to either a first supply voltage (from the first supply voltage node) or the second supply voltage (from the second supply voltage node). For example, the first supply voltage may be an analog supply voltage for an analog power domain, while the second supply voltage may be a supply voltage for digital circuitry in the second power domain. The analog supply voltage may, in various embodiment, be greater than the second supply voltage provided to the digital circuitry in the second (digital) power domain. When the first supply voltage is powered down, the second supply voltage may be provided to the third supply voltage node. When the first supply voltage is initially powered on, the cross-domain power control circuit may begin ramping up the voltage on the third supply voltage node. When the analog supply voltage is fully powered on and ready, the cross-domain power control circuit may then electrically couple the first supply voltage to the third supply voltage node. Digital logic within the first power domain may then be used to control switches of a switching network for the transfer of signals between the digital and analog power domains.

When the analog power domain is to be powered down, the circuit disclosed herein may operate to ramp down the voltage on the third supply voltage node from the analog supply voltage to the second (digital) supply voltage. When the analog supply voltage has been fully powered down, the third supply voltage node may receive the second supply voltage.

Turning now to FIG. 1, a schematic diagram of one embodiment of a cross-domain power control circuit is illustrated. In the embodiment shown, power controller 100 includes a first circuit branch (including MN1, MN2, and MN3, which are NMOS devices) and a second circuit branch (including MN4, MN5, and MN6, also NMOS devices) that are each coupled to receive a first supply voltage VddH. In some embodiments, VddH may be an analog supply voltage, e.g., used to supply analog circuitry. For example, the analog circuitry may implement an on-chip measurement system used to measure various operating parameters of an integrated circuit. The circuit of FIG. 1 also includes a third circuit branch (including MP1, a PMOS device) coupled to receive a second supply voltage, VddL. A fourth circuit branch (including MN7, another NMOS device) is coupled to receive the first supply voltage. In one embodiment, the supply voltage VddL may be less than VddH, and may be used to supply digital circuitry in a second power domain.

The third and fourth circuit branches of power controller 100 are each coupled to a third supply voltage node, VddNew. In the third circuit branch, transistor MP1 is coupled between VddL and VddNew. In the fourth circuit branch, MN7 is coupled between VddH and VddNew. These transistors may be implemented as devices having very low threshold voltages. Accordingly, when MN7 is active (and MP1 is inactive), the voltage present on VddNew may be substantially equal to that of VddH, with a small (if not negligible) difference accounted for by the threshold voltage of MN7. When MP1 is active (and MN7 is inactive, VddNew may be substantially equal to VddL.

Power controller 100 in the embodiment shown also includes control circuitry 105, which includes inverters Inv1, Inv2, and Inv3. Inverter Inv1 includes an input which may receive the control signal VddH_Ready, which may be provided from a power management circuit (discussed below). Depending on the state of VddH_Ready (asserted or de-asserted), one of MP1 or MN7 may be activated.

A first mode of operation may occur when VddH_Ready is asserted while VddH is powered up. If VddH_Ready is high (corresponding to an asserted state in this embodiment) and VddH is powered up, the output of inverter Inv1 is low, while the output of Inv2 and Inv3 are high. When the output of Inv3 is high, MN6 is held inactive, since its source voltage is approximately the same as its gate voltage (VddL) in this case. Thus, the gate-source voltage across MN6 is insufficient for activation. Since there is no active pull-down path through this circuit branch when MN6 is inactive, MN4, which is diode-coupled in this embodiment, pulls VGN high (to within a threshold voltage of VddH and thereafter by the subthreshold current VGN is raised to very close to the level of VddH), thus activating MN7. As shown in the drawing, VGN is the voltage present on the gate terminal of MN7, and is also tied to the source of MN4 and gate/drain terminals of diode-coupled MN5. As previously noted, MN7 may be implemented with a low threshold voltage. The activation of MN7 thus causes VddNew to be pulled up to a voltage that is substantially that of VddH, the only difference being the small threshold voltage. Meanwhile, the high output from Inv2 causes MN3 to be held inactive, since this case results in the gate and source voltages of this device being substantially equal and thus the gate-source voltage is insufficient for activation. Accordingly, the circuit branch of MN3 provides no pull-down path. Transistor MN1, diode-coupled in this case, thus pulls VGP high, thereby preventing the activation of PMOS device MP1 (VGP being the voltage on the gate terminal of MP1, and also coupled to the source terminal of MN1 and the gate/drain terminals of diode-coupled MN2). Accordingly, VddL is isolated from VddNew in this mode of operation.

Another mode of operation occurs when VddH is powered down and VddH_Ready is de-asserted (low in this embodiment). When VddH_Ready is low, the output of Inv1 is high, while the outputs of Inv2 and Inv3 are low. When Inv2 is low, MN3 is activated as the gate-source voltage across this device exceeds the threshold in this case. This in turn activates a pull-down path in this circuit branch, through MN2, MN3, and Inv2. As a result, VGP is pulled low, causing activation of MP1. When MP1 is active, the supply voltage VddL is conveyed to VddNew. Meanwhile, the low output from Inv3 causes MN6 to be active. With MN6 active, there is a pull-down path through its corresponding circuit branch. Thus, VGN is also pulled low, inhibiting activation of MN7. VddH is thus isolated form VddNew in this mode of operation.

In addition to the modes described above, power controller 100 may operate in two additional modes, a ramp-up mode (which includes a transition of VddH from powered down to powered up) and a ramp-down mode (which includes a transition of VddH from powered up to powered down). These modes will be discussed in further detail below with reference to the timing diagram of FIG. 4.

FIG. 2 is a schematic diagram illustrating an arrangement of a cross-domain power control circuit in the context of two power domains. In the embodiment shown, integrated circuit 20 includes two power domains, VddL Domain and VddH Domain. Although not explicitly shown here, the VddL Domain may include various digital circuits, some of which may transfer signals to the VddH Domain. Similarly, while not explicitly shown here, the VddH Domain may include various analog circuits that may receive some signal input from digital circuitry in the VddL Domain.

As shown here, a switch network of passgates (PG1, PG2, PG3, and PG4) is implemented in the VddH Domain. Power controller 100 in the embodiment shown is implemented across the power domains and provides voltage VddNew into the VddNew domain. Absent power controller 100, the problems described above may occur when VddH is powered down, as certain devices used to implement the passgates (e.g., the PMOS devices) may not be able to be fully turned off. In particular the signals crossing the power domains into the switch network may be effectively shorted to the analog domain by passgates PG1-PG4, as the passgates are turned on in the absence of the analog power supply when power controller 100 is absent. Generating VddNew using power controller 100 and using the digital logic 207 in the VddNew Domain may enable each device of the passgates to be fully turned off such that these problems do not occur.

It is noted that the various signals shown as provided to passgates PG1-PG4 (VddL, ground, Tx1 via way of buffer B1, and Tx2 by way of buffer B2) are provided as examples, and do not necessarily represent the actual types of signals that are passed between the VddL and the VddH domains.

Integrated circuit 20 includes one or more level shifters 203, which are coupled to receive one or more corresponding digital input signals (‘Digital In’). Level shifters 203 may, when VddNew is substantially equal to VddH, perform a level shifting operation for signals input from the VddL domain to the VddNew domain. Otherwise, when VddNew is substantially equal to VddL, signals may be conveyed through level shifters 203 with the same levels on the outputs as at the inputs.

Digital logic 207 may receive the digital signals from level shifters 203. Among the functions of digital logic 207 is to output one or more signals to generate enable signals (En[0]-En[3]) and their complements (Enb[0]-Enb[3]) by inverters Inv201 and Inv202. When VddNew is substantially equal to VddL, digital logic 207 generates signals levels such that the correspondingly generate enable signals may fully shut down the devices that implement passgates PG1-PG4. This may in turn prevent the occurrence of those problems outlined above.

In the embodiment shown, IC 20 in the embodiment shown includes power management circuit 202. Among the functions of power management circuit is to control the powering up and powering down of the supply to VddH, which is discussed in further detail below. Additionally, power management circuit 202 also generates the VddH_Ready signal provided to power controller 100. When VddH is powered on, power management circuit 202 may assert the VddH_Ready signal once VddH is fully powered on and stable. Similarly, power management circuit 202 may de-assert the VddH_Ready signal during the power down of VddH. The assertion and de-assertion of VddH_Ready causes changes to the state of power controller 100 as discussed above in reference to FIG. 1.

FIG. 3 is a block diagram illustrating first and second power domains and circuitry coupling the two. In the embodiment shown, integrated circuit 30 includes a number of the same elements as integrated circuit 20 of FIG. 2, including a power management circuit 202, level shifters 203, digital logic 207, inverters Inv201 and Inv203, and power controller 100. Integrated circuit 30 in the embodiment shown also includes a switch network 311, which may be implemented in a manner similar to that of the passgates shown in FIG. 2. A digital subsystem 305 is implemented in the VddL domain, and may include a number of different digital circuits that perform various functions carried out by integrated circuit 30. An analog subsystem 310 is implemented in in the VddH domain, and may include various types of analog circuitry.

In the embodiment shown, integrated circuit 30 also includes a voltage regulator 304. Since VddH is greater than VddL in this embodiment, voltage regulator 304 is a boost voltage regulator. Furthermore, voltage regulator 304 is implemented as a low dropout (LDO) voltage regulator in this embodiment.

Power management circuit 202 in the embodiment shown may control the status of VddH (powered up or powered down) through the signal VddH_On_Off provided to voltage regulator 304. When VddH_On_Off is asserted, VddH may be powered up, while VddH may be powered down when VddH_On_Off is de-asserted. Power management circuit 202 in the embodiment shown assert and de-assert the VddH_Ready signal in conjunction of assertion/de-assertion of the VddH_On_Off signal in controlling the various modes of power controller 100.

FIG. 4 is a timing diagram illustrating various modes of operation of one embodiment of a cross-domain power control circuit. More particularly, the timing diagram of FIG. 4 illustrates four different modes of operation for various embodiments of power controller 100 as discussed above.

In the illustrated example, power controller 100 operates in the VddL mode when VddL is powered on while VddH is powered down. It is also noted that in the VddL mode, the Enb signals (EnB[0] is shown here) are held at the substantially the same level as VddL, while the En signals (En[0] is shown here) is held substantially to zero volts. In embodiments utilizing passgates, such as that shown in FIG. 2, this holds the passgates in an off state, as the EnB signals at VddL cause the PMOS device in each passgate to be off, while the low En signals hold the NMOS device in each passgate as off. Additionally, in the VddL mode, the voltage of VddNew is substantially the same as VddL.

In the Ramp Up mode, VddH is turned on and begins powering up. Responsive to the ramping up of VddH, VddNew also ramps up, initially to an intermediate voltage, Vdd_M. This intermediate voltage is greater than VddL but less than VddH. In the Ramp Up mode, VGN is determined by the voltage division of the diodes formed by the coupling of MN4 and MN5. VddNew is very close to VGN (within one threshold of VGN). The EnB signals also ramp up to Vdd_M. At the end of the Ramp Up mode, when VddH is fully powered up and stable, the VddH_Ready signal is asserted, causing entry into the VddH mode.

Responsive to assertion of the VddH_Ready signal, VddNew transitions to a voltage that is substantially the same as VddH. Similarly, the EnB signals initially transition to this voltage. Thereafter, the En and EnB signals may be toggled as desired to enable or disable various switches of a switch network through which signals can be transferred between the VddH and VddL domains.

Exit from the VddH mode and into the Ramp Down mode occurs responsive to de-assertion of the VddH_Ready signal. This de-assertion occurs prior to commencing the power down of VddH. Upon initially de-asserting VddH_ready, VddNew falls back to the intermediate voltage Vdd_M. VddH may then begin the power down, as this voltage is ramped down. As a result of the ramping down of VddH, Vdd_New also ramps down from Vdd_M, eventually reaching VddL. Similarly, the EnB signals also ramp down in concert with VddNew. Upon VddNew reaching VddL, the power controller returns to the VddL mode.

FIG. 5 is a flow diagram illustrating one embodiment of a method for operating a cross-domain power control circuit. Method 500 as shown here may be performed by various embodiments of the circuitry/hardware discussed above. Additionally, hardware/circuit embodiments not explicitly disclosed herein may also be capable of performing method 500, and may thus fall within the scope of this disclosure.

Method 500 begins with generating, using a voltage regulator, a first supply voltage for a first power domain, wherein the first supply voltage is generated based on a second supply voltage of a second power domain, and wherein the first supply voltage is greater than the second supply voltage, wherein the first supply voltage is conveyed on a first supply voltage node and the second supply voltage is conveyed on a second supply voltage node (block 505). The method further includes operating a power controller circuit in a first mode, wherein operating in the first mode comprises a control circuitry causing a first circuit branch of the cross-domain power circuit to activate a first transistor to convey the second supply voltage to a third supply voltage node (block 510). Operating the power controller circuit in a second mode comprises the control circuitry causing a second circuit branch of the cross-domain power circuit to activate a second transistor to convey the first supply voltage to the third supply voltage node (block 515).

In some embodiments, the method includes operating the power controller circuit in a third mode. Operating the power controller circuit in the third mode in such embodiments includes causing the voltage regulator to power up the first supply voltage node to the first supply voltage using a power management circuit. Operating in the third mode also includes asserting a control signal provided from the power management circuit to the control circuitry. Thereafter, operation in the third mode includes deactivating the first transistor responsive to asserting the control signal, wherein deactivating the first transistor causes discontinuation of providing the second supply voltage to the third supply voltage node, and activating the second transistor responsive to asserting the control signal. Operation in the third mode also includes causing the first supply voltage to be provided to the third supply voltage node responsive to activating the second transistor.

Various embodiments also include operating the power controller circuit in a fourth mode. Operating the power controller circuit in the fourth mode comprises de-asserting the control signal and deactivating the second transistor responsive to de-asserting the control signal. Operating in the fourth mode also includes activating the first transistor responsive to asserting the control signal and causing the second supply voltage to be provided on the third supply voltage node responsive to activating the first transistor.

Turning next to FIG. 6, a block diagram of one embodiment of a system 150 is shown. In the illustrated embodiment, the system 150 includes at least one instance of an integrated circuit 10 coupled to external memory 158. The integrated circuit 10 may include a memory controller that is coupled to the external memory 158. The integrated circuit 10 is coupled to one or more peripherals 154 and the external memory 158. A power supply 156 is also provided which supplies the supply voltages to the integrated circuit 10 as well as one or more supply voltages to the memory 158 and/or the peripherals 154. In some embodiments, more than one instance of the integrated circuit 10 may be included (and more than one external memory 158 may be included as well).

The peripherals 154 may include any desired circuitry, depending on the type of system 150. For example, in one embodiment, the system 150 may be a mobile device (e.g. personal digital assistant (PDA), smart phone, etc.) and the peripherals 154 may include devices for various types of wireless communication, such as WiFi, Bluetooth, cellular, global positioning system, etc. The peripherals 154 may also include additional storage, including RAM storage, solid-state storage, or disk storage. The peripherals 154 may include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, the system 150 may be any type of computing system (e.g. desktop personal computer, laptop, workstation, tablet, etc.).

The external memory 158 may include any type of memory. For example, the external memory 158 may be SRAM, dynamic RAM (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, etc.) SDRAM, RAMBUS DRAM, etc. The external memory 158 may include one or more memory modules to which the memory devices are mounted, such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc.

In various embodiment of system 150, integrated circuit 10, or other integrated circuits implemented within various ones of peripherals 154 may include multiple power domains (e.g., similar to IC 20 of FIG. 2 and/or IC 30 of FIG. 3). Thus, such embodiments may also include various embodiments of a cross-domain power controller and other circuits discussed above.

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications. 

What is claimed is:
 1. A circuit comprising: a first circuit branch having a first transistor coupled to receive a first supply voltage from a first supply voltage node; a second circuit branch having a second transistor coupled to receive the first supply voltage; a third circuit branch having a third transistor coupled between a second supply voltage node and a third supply voltage node, wherein a second supply voltage conveyed on the second supply voltage node is less than the first supply voltage; a fourth circuit branch having a fourth transistor coupled between the first supply voltage node and the third supply voltage node; and control circuitry configured to, when the circuit is operating in a first mode, cause the first circuit branch to activate the third transistor to convey the second supply voltage to the third supply voltage node, and further configured to, when the circuit is operating in a second mode, cause the second circuit branch to activate the fourth transistor to convey the first supply voltage to the third supply voltage node.
 2. The circuit of claim 1, wherein the first, second, and fourth transistors are diode-coupled transistors.
 3. The circuit of claim 1, wherein the first transistor is diode-coupled, and wherein the first circuit branch further comprises: a fifth transistor, wherein the fifth transistor is a diode-coupled transistor having gate and drain terminals coupled to a source terminal of the first transistor; and a sixth transistor having a drain terminal coupled to a source terminal of the fifth transistor and a gate terminal coupled to the second supply voltage node, wherein a source terminal of the second transistor is coupled to receive a first output signal generated by the control circuitry.
 4. The circuit of claim 3, wherein the second transistor is diode-coupled, and wherein the second circuit branch further includes: a seventh transistor, wherein the seventh-transistor is a diode-coupled transistor having gate and drain terminals coupled to a source terminal of the second transistor; and an eighth transistor having a drain terminal coupled to a source terminal of the seventh transistor, a gate terminal coupled to the second supply voltage node, and a source terminal coupled to receive a second output signal generated by the control circuitry.
 5. The circuit of claim 3, wherein the third transistor includes a gate terminal coupled to a source terminal of the first transistor, a source terminal coupled to the second supply voltage node, and a drain terminal coupled to the third supply voltage node.
 6. The circuit of claim 3, wherein the fourth transistor includes a gate terminal coupled to a source terminal of the second transistor, a drain terminal coupled to the first supply voltage node, and a source terminal coupled to the third supply voltage node.
 7. The circuit of claim 1, wherein the circuit is configured to operate in a third mode responsive to a power management circuit causing the first supply voltage node to transition from a power down state to a power up state, wherein during operation in the second mode, the third supply voltage node is configured to transition from the second supply voltage to an intermediate voltage, and responsive to assertion of a control signal to the control circuitry, transition from the intermediate voltage to the first supply voltage.
 8. The circuit of claim 1, wherein the circuit is further configured to operate in a fourth mode, wherein responsive to de-assertion of a control signal, the third voltage node is configured to transition from the first supply voltage to an intermediate voltage, and subsequently transition from the intermediate voltage to the second supply voltage responsive to powering down the first supply voltage node.
 9. The circuit of claim 1, further comprising a power management circuit configured to control a power state of the first supply voltage, and further configured to provide a control signal to the control circuitry.
 10. The circuit of in claim 1, further comprising a voltage regulator configured to generate the first supply voltage based on receiving the second supply voltage.
 11. A method comprising: generating, using a voltage regulator, a first supply voltage for a first power domain, wherein the first supply voltage is generated based on a second supply voltage of a second power domain, and wherein the first supply voltage is greater than the second supply voltage, wherein the first supply voltage is conveyed on a first supply voltage node and the second supply voltage is conveyed on a second supply voltage node; operating a power controller circuit in a first mode, wherein operating in the first mode comprises a control circuitry causing a first circuit branch of the cross-domain power circuit to activate a first transistor to convey the second supply voltage to a third supply voltage node; and operating the power controller circuit in a second mode, wherein operating in the second mode comprises the control circuitry causing a second circuit branch of the cross-domain power circuit to activate a second transistor to convey the first supply voltage to the third supply voltage node.
 12. The method of claim 11, further comprising operating the power controller circuit in a third mode, wherein operating the power controller circuit in the third mode comprises: causing the voltage regulator to power up the first supply voltage node to the first supply voltage using a power management circuit; asserting a control signal provided from the power management circuit to the control circuitry; deactivating the first transistor responsive to asserting the control signal, wherein deactivating the first transistor causes discontinuation of providing the second supply voltage to the third supply voltage node; activating the second transistor responsive to asserting the control signal; and causing the first supply voltage to be provided to the third supply voltage node responsive to activating the second transistor.
 13. The method of claim 12, further comprising operating the power controller circuit in a fourth mode, wherein operating the power controller circuit in the fourth mode comprises: de-asserting the control signal; deactivating the second transistor responsive to de-asserting the control signal; activating the first transistor responsive to asserting the control signal; and causing the second supply voltage to be provided on the third supply voltage node responsive to activating the first transistor.
 14. An integrated circuit comprising: a first power domain comprising circuitry coupled to receive a first supply voltage via a first supply voltage node; a second power domain comprising circuitry coupled to receive a second supply voltage via second supply voltage node; and a power controller circuit comprising a third supply voltage node, wherein the power controller circuit includes control circuitry configured to, when operating in a first mode, cause activation of a first transistor to convey the second supply voltage to a third supply voltage node, wherein the control circuitry is further configured to, when operating in a second mode, cause activation of a second transistor to convey the first supply voltage to the third supply voltage node.
 15. The integrated circuit of claim 14, further comprising a power management circuit, wherein the power management circuit is configured to provide a control signal to the control circuitry of the power controller circuit, and further configured to control whether the first supply voltage is powered on.
 16. The integrated circuit of claim 15, wherein responsive to receiving the control signal in an asserted state, the control circuitry is configured to: cause a first circuit branch to deactivate the first transistor, wherein the first transistor is implemented in a second circuit branch; and cause a third circuit branch to activate the second transistor, wherein the second transistor is implemented in a fourth circuit branch.
 17. The integrated circuit of claim 16, wherein responsive to receiving the control signal in a de-asserted state, the control circuitry is configured to: cause the first circuit branch to activate the first transistor; and cause the third circuit branch to de-activate the second transistor.
 18. The integrated circuit of claim 14, further comprising a voltage regulator configured to generate the first supply voltage based on receiving the second supply voltage, wherein the first supply voltage is greater than the second supply voltage.
 19. The integrated circuit of claim 14, wherein the power controller circuit is further configured to operate in a third mode responsive to a power management circuit causing the first supply voltage node to be powered on and subsequently asserting a control signal to the control circuitry, wherein operating in the third mode comprises increasing a voltage present on the third supply voltage node from the second supply voltage to an intermediate voltage, and subsequently increasing the voltage on the third supply voltage node to the first supply voltage.
 20. The integrated circuit of claim 14, wherein the power controller circuit is further configured to operate in a fourth mode responsive to a power management circuit de-asserting a control signal provided to the control circuitry and subsequently powering down the first supply voltage node, wherein operating in the fourth mode comprises reducing a voltage present on the third supply voltage node from the first supply voltage to an intermediate voltage responsive to de-asserting the control signal, and subsequently reducing the voltage on the third supply voltage node to the second supply voltage. 